In semiconductor manufacturing, a low-k dielectric is a material with a small dielectric constant relative to silicon dioxide. Silicon dioxide has a k value of 3.9. Materials with k values less than 3.9 are considered low-k dielectric materials. In digital circuits, insulating dielectrics separate interconnects and transistors from one another. As integrated circuits have minimized, components have scaled correspondingly and the insulating dielectrics have thinned to the point where charge build up and crosstalk adversely affect the performance of the circuit. Replacing the silicon dioxide with a low-k dielectric reduces parasitic capacitance, enabling faster switching speeds and lower heat dissipation.
Dual damascene processing is a method for fabricating planar interconnects. Damascene wiring interconnects are formed by depositing a dielectric layer on a planar surface, patterning the dielectric layer using photolithography and etching, then filling the recesses with conductive metal, often copper (Cu). The excess metal is removed by chemical mechanical polishing (CMP), while the trenches or channels remain filled with metal. In the damascene processing approach, the deposited conductive metal is deposited into a patterned insulator, typically a low-k dielectric. This is desirable because mask alignment, dimensional control, rework, and the etching process are all easier when applied to a dielectric rather than metal films. Damascene processing achieves these benefits by shifting the enhanced filling and planarization requirements from dielectric to metal films, and by shifting control over interconnect thickness from metal deposition to insulator patterning and metal CMP.
The low-k dielectric used in the damascene process is susceptible to damage during the damascene etch process. In particular, the low-k dielectric is vulnerable to damage during etch, photoresist ashing and etch by-product, such as polymer-like residue stripping steps. Damage to the low-k dielectric layer is generated during processing because of carbon loss. This damage may cause a higher capacitance and therefore degrade device performance.
The speed at which a signal is propagated in an integrated circuit is limited by the delay through the metal line carrying the signal. This delay, commonly known as “RC delay,” is determined by the product of the resistance (R) and capacitance (C) of the metal line and the interconnections between conductors. Reducing the resistance and/or capacitance of a metal line lowers its RC delay and increases signal propagation speed. Therefore, reducing the RC delay of metal lines plays a major role in making integrated circuits run faster.